By Willy Sansen (auth.), Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto (eds.)

ISBN-10: 9400719256

ISBN-13: 9789400719255

Analog Circuit layout comprises the contribution of 18 tutorials of the twentieth workshop on Advances in Analog Circuit layout. every one half discusses a selected to-date subject on new and helpful layout rules within the region of analog circuit layout. every one half is gifted through six specialists in that box and cutting-edge details is shared and overviewed. This booklet is quantity 20 during this profitable sequence of Analog Circuit layout, delivering necessary details and perfect overviews of:

Topic 1 : Low Voltage Low strength, chairman: Andrea Baschirotto
Topic 2 : brief variety instant Front-Ends, chairman: Arthur van Roermund
Topic three : energy administration and DC-DC, chairman : Michiel Steyaert.
Analog Circuit layout is an important reference resource for analog circuit designers and researchers wishing to maintain abreast with the newest improvement within the box. the educational assurance additionally makes it compatible to be used in a complicated layout course.

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Additional info for Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

Sample text

The architecture depicted in Fig. g. downward. 3 Low-Power Successive Approximation ADCS for Wireless Applications 43 Fig. 4 (a) Monotonic capacitor switching architecture; (b) typical waveforms [7] The input is sampled on the top plates, while at the same time the bottom plates of the capacitors are reset to VREF . Next, the comparator directly performs the first comparison without switching any capacitor. According to the comparator output, the largest capacitor C1 on the higher voltage potential side is switched to ground and the other one (on the lower side) remains unchanged.

This residue is amplified by a resistively loaded transconductance stage to produce the desired full-swing residue voltage Vres . Since the high gain requirement in the transconductor is now dropped, a basic differential pair-type stage can be used to replace the complex amplifier in Fig. 4. g. [51, 52], and the current mode topology of [53]. The circuit in Fig. 10b [54] samples the input on two capacitors connected in parallel. Next, it stacks the capacitors in series to achieve a voltage gain of two.

IEEE J. Solid-State Circuits 40(5), 1038–1046 (2005) 60. A. Panigada, I. Galton, A 130 mW 100 MS/s pipelined ADC with 69 dB SNDR enabled by digital harmonic distortion correction. IEEE J. Solid-State Circuits 44(12), 3314–3328 (2009) 61. D. Sahoo, B. Razavi, A 12-bit 200-MHz CMOS ADC. IEEE J. Solid-State Circuits 44(9), 2366–2380 (2009) 62. M. , A 14-bit 20-MS/s pipelined ADC with digital distortion calibration. IEEE J. Solid-State Circuits 41(11), 2417–2423 (2006) 38 B. Murmann 63. B. E. Boser, Digital domain measurement and cancellation of residue amplifier nonlinearity in pipelined ADCs.

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Analog Circuit Design: Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC by Willy Sansen (auth.), Michiel Steyaert, Arthur van Roermund, Andrea Baschirotto (eds.)


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